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august 3, 2004 ? cypress microsystems, inc. 2002 ? 2004 ? document no. 38-12012 rev. *i 1 psoc? mixed signal array final data sheet cy8c27143, cy8c27243, cy8c27443, cy8c27543, and cy8c27643 psoc? functional overview the psoc? family consists of many mixed signal array with on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, as well as programmable interconnects. this architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of conve- nient pinouts and packages. the psoc architecture, as illustrated on the left, is comprised of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows all the device resources to be combined into a complete custom system. the psoc cy8c27x43 family can have up to five io ports that connect to the global digital and analog interconnects, providing access to 8 digital blocks and 12 analog blocks. the psoc core the psoc core is a powerful engine that supports a rich fea- ture set. the core includes a cpu, memory, clocks, and config- urable gpio (gene ral purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micro- features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3.0 to 5.25 v operating voltage ? operating voltages down to 1.0v using on- chip switch mode pump (smp) ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? 12 rail-to-rail analog psoc blocks provide: - up to 14-bit adcs - up to 9-bit dacs - programmable gain amplifiers - programmable filters and comparators ? 8 digital psoc blocks provide: - 8- to 32-bit timers, counters, and pwms - crc and prs modules - up to 2 full-duplex uarts - multiple spi ? masters or slaves - connectable to all gpio pins ? complex peripherals by combining blocks precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? 24/48 mhz with optional 32 khz crystal ? optional external oscillator, up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 16k bytes flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 12 analog inputs on gpio ? four 30 ma analog outputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc? designer) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory digital system sram 256 bytes interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array multiply accum. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref analog input muxing i c 2 (2 rows, 8 blocks) port 4 port 3 port 2 port 1 port 0 analog drivers system bus analog block array (4 columns, 12 blocks) port 5
august 3, 2004 document no. 38-12012 rev. *i 2 cy8c27x43 final data sheet psoc? overview processor. the cpu utilizes an interrupt controller with 17 vec- tors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watch dog timers (wdt). memory encompasses 16 kb of flash for program storage, 256 bytes of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash utilizes four protec- tion levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock genera- tors, including a 24 mhz imo (internal main oscillator) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crys- tal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfac- ing. every pin also has the capability to generate a system inter- rupt on high level, low level, and change from last read. the digital system the digital system is composed of 8 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital system block diagram digital peripheral configurations include those listed below. pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity (up to 2) spi master and slave (up to 2) i2c slave and master (1 available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to 2) pseudo random sequence generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the con- straints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the opti- mum choice of system resources for your application. family resources are shown in the table titled ?psoc device charac- teristics? on page 3 . the analog system the analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexi- ble and can be customized to support specific application requirements. some of the more common psoc analog func- tions (most available as user modules) are listed below. analog-to-digital converters (up to 4, with 6- to 14-bit resolu- tion, selectable as incremental, delta sigma, and sar) filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 4, with 16 selectable thresholds) dacs (up to 4, with 6- to 9-bit resolution) multiplying dacs (up to 4, with 6- to 9-bit resolution) high current output drivers (four with 30 ma drive as a core resource) 1.3v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 4 port 3 port 2 port 1 port 0 port 5
august 3, 2004 document no. 38-12012 rev. *i 3 cy8c27x43 final data sheet psoc? overview analog blocks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as shown in the figure below. analog system block diagram additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. addi- tional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. brief state- ments describing the merits of each system resource are pre- sented below. digital clock dividers provide three customizable clock fre- quencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following table lists the resources available for specific psoc device groups. the psoc device covered by this data sheet is shown in the second row of the table. acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandga p refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks cy8c29x66 up to 64 4 16 12 4 4 12 cy8c27x43 up to 44 2 8 12 4 4 12 cy8c24x23 up to 24 1 4 12 2 2 6 cy8c24x23a up to 24 1 4 12 2 2 6 cy8c22x13 up to 16 1 4 8 1 1 3
august 3, 2004 document no. 38-12012 rev. *i 4 cy8c27x43 final data sheet psoc? overview getting started the quickest path to understanding the psoc silicon is by read- ing this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an over- view of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc? mixed signal array technical reference manual . for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com/psoc. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store at http://www.onfulfillment.com/cypressstore/ contains develop- ment kits, c compilers, and all accessories for psoc develop- ment. click on psoc (programmable system-on-chip) to view a current list of available items. tele-training free psoc "tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes cover- ing topics like psoc and the lin bus. for days and times of the tele-training, see http://www.cypress.com/support/training.cfm . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant, go to the following cypress support web site: http://www.cypress.com/support/cypros.cfm . technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to locate the psoc application notes, go to http://www.cypress.com/design/results.cfm . development tools the cypress microsystems psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, win- dows 2000, windows millennium (me), or windows xp. (refer- ence the psoc designer functional flow diagram below.) psoc designer helps the customer to select an operating con- figuration for the psoc, write application code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. psoc designer subsystems commands results psoc tm designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc tm designer
august 3, 2004 document no. 38-12012 rev. *i 5 cy8c27x43 final data sheet psoc? overview psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configu- ration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports cypress microsystems? psoc family devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of the parallel or usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation.
august 3, 2004 document no. 38-12012 rev. *i 6 cy8c27x43 final data sheet psoc? overview designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the io pins. iterative development cycles permit you to adapt the hard- ware as well as the software. this substantially lowers the risk that you will have to select a different part to meet the final design requirements. to speed the development process, the psoc designer inte- grated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library con- tains over 50 common peripherals such as adcs, dacs tim- ers, counters, uarts, and other not-so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user mod- ule configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high- level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service rou- tines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the set- ting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. user module and source code development flows the next step is to write your main program, and any sub-rou- tines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all gener- ated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a profes- sional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as nec- essary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger down- loads the hex image to the in-circuit emulator (ice) where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator
august 3, 2004 document no. 38-12012 rev. *i 7 cy8c27x43 final data sheet psoc? overview document conventions acronyms used the following table lists the acronyms that are used in this doc- ument. units of measure a units of measure table is located in the electrical specifica- tions section. table 3-1 on page 17 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimal. table of contents for an in depth discussion and more information on your psoc device, obtain the psoc mixed signal array technical refer- ence manual . this document encompasses and is organized into the following chapters and sections. 1. pin information ............................................................. 8 1.1 pinouts ................................................................... 8 1.1.1 8-pin part pinout .................................................8 1.1.2 20-pin part pinout ...............................................9 1.1.3 28-pin part pinout .............................................10 1.1.4 44-pin part pinout .............................................11 1.1.5 48-pin part pinouts ...........................................12 2. register reference ..................................................... 14 2.1 register conventions ........................................... 14 2.2 register mapping tables ..................................... 14 3. electrical specifications ............................................ 17 3.1 absolute maximum ratings ................................ 18 3.2 operating temperature ....................................... 18 3.3 dc electrical characteristics ................................ 19 3.3.1 dc chip-level specifications .............................19 3.3.2 dc general purpose io s pecifications ..............19 3.3.3 dc operational amplifier specifications ............20 3.3.4 dc analog output buffer specifications ............22 3.3.5 dc switch mode pump specifications ...............23 3.3.6 dc analog reference specif ications .................24 3.3.7 dc analog psoc block specifications ...............26 3.3.8 dc por and lvd specifications .......................26 3.3.9 dc programming specifications ........................27 3.4 ac electrical characteristics ................................ 28 3.4.1 ac chip-level specifications .............................28 3.4.2 ac general purpose io specifications ..............30 3.4.3 ac operational amplifier specifications .............31 3.4.4 ac digital block specifications ..........................32 3.4.5 ac analog output buffer specifications .............33 3.4.6 ac external clock specifications .......................34 3.4.7 ac programming specifications .........................34 3.4.8 ac i2c specifications .........................................35 4. packaging information ............................................... 36 4.1 packaging dimensions ......................................... 36 4.2 thermal impedances .......................................... 41 4.3 capacitance on crystal pins ............................... 41 5. ordering information .................................................. 42 5.1 ordering code definitions ................................... 43 6. sales and service information .................................. 44 6.1 revision history ................................................... 44 6.2 copyrights and code protection .......................... 44 acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator ram random access memory sc switched capacitor slimo slow imo smp switch mode pump
august 3, 2004 document no. 38-12012 rev. *i 8 1. pin information this chapter describes, lists, and illustrates the cy8c27x43 psoc device pins and pinout configurations. 1.1 pinouts the cy8c27x43 psoc device is available in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital io. however, vss, vdd, smp, and xres are not capable of digital io. 1.1.1 8-pin part pinout table 1-1. 8-pin part pinout (pdip) pin no. type pin name description cy8c27143 8-pin psoc device digital analog 1 io io p0[5] analog column mux input and column output. 2 io io p0[3] analog column mux input and column output. 3 io p1[1] crystal input (xtalin), i2c serial clock (scl) 4 power vss ground connection. 5 io p1[0] crystal output (xtalout), i2c serial data (sda) 6 io io p0[2] analog column mux input and column output. 7 io io p0[4] analog column mux input and column output. 8 power vdd supply voltage. legend : a = analog, i = input, and o = output. pdip 1 2 3 4 aio, p0[5] aio, p0[3] i2c scl, xtalin, p1[1] vss 8 7 6 5 vdd p0[4], aio p0[2], aio p1[0], xtalout, i2c sd a
august 3, 2004 document no. 38-12012 rev. *i 9 cy8c27x43 final data sheet 1. pin information 1.1.2 20-pin part pinout table 1-2. 20-pin part pinout (ssop, soic) pin no. type pin name description cy8c27243 20-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 power smp switch mode pump (smp) connection to external components required. 6 io p1[7] i2c serial clock (scl) 7 io p1[5] i2c serial data (sda) 8 io p1[3] 9 io p1[1] crystal input (xtalin) , i2c serial clock (scl) 10 power vss ground connection. 11 io p1[0] crystal output (xtalout), i2c serial data (sda) 12 io p1[2] 13 io p1[4] optional external clock input (extclk) 14 io p1[6] 15 input xres active high external reset with internal pull down. 16 io i p0[0] analog column mux input. 17 io io p0[2] analog column mux input and column output. 18 io io p0[4] analog column mux input and column output. 19 io i p0[6] analog column mux input. 20 power vdd supply voltage. legend : a = analog, i = input, and o = output. ssop soic vdd p0[6], ai p0[4], aio p0[2], aio p0[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sd a 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss
august 3, 2004 document no. 38-12012 rev. *i 10 cy8c27x43 final data sheet 1. pin information 1.1.3 28-pin part pinout table 1-3. 28-pin part pinout (pdip, ssop, soic) pin no. type pin name description cy8c27443 28-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 power smp switch mode pump (smp) connection to external components required. 10 io p1[7] i2c serial clock (scl) 11 io p1[5] i2c serial data (sda) 12 io p1[3] 13 io p1[1] crystal input (xtalin) , i2c serial clock (scl) 14 power vss ground connection. 15 io p1[0] crystal output (xta lout), i2c serial data (sda) 16 io p1[2] 17 io p1[4] optional external clock input (extclk) 18 io p1[6] 19 input xres active high external reset with internal pull down. 20 io i p2[0] direct switched capacitor block input. 21 io i p2[2] direct switched capacitor block input. 22 io p2[4] external analog ground (agnd) 23 io p2[6] external voltage reference (vref) 24 io i p0[0] analog column mux input. 25 io io p0[2] analog column mux input and column output. 26 io io p0[4] analog column mux input and column output. 27 io i p0[6] analog column mux input. 28 power vdd supply voltage. legend : a = analog, i = input, and o = output. ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[7] p2[5] ai, p2[3] ai, p2[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd p0[6], ai p0[4], aio p0[2], aio p0[0], ai p2[6], external vref p2[4], external agnd p2[2], ai p2[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sd a pdip ssop soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
august 3, 2004 document no. 38-12012 rev. *i 11 cy8c27x43 final data sheet 1. pin information 1.1.4 44-pin part pinout table 1-4. 44-pin part pinout (tqfp) pin no. type pin name description cy8c27543 44-pin psoc device digital analog 1 io p2[5] 2 io i p2[3] direct switched capacitor block input. 3 io i p2[1] direct switched capacitor block input. 4 io p4[7] 5 io p4[5] 6 io p4[3] 7 io p4[1] 8 power smp switch mode pump (smp) connection to external components required. 9 io p3[7] 10 io p3[5] 11 io p3[3] 12 io p3[1] 13 io p1[7] i2c serial clock (scl) 14 io p1[5] i2c serial data (sda) 15 io p1[3] 16 io p1[1] crystal input (xtalin), i2c serial clock (scl) 17 power vss ground connection. 18 io p1[0] crystal output (xtalout), i2c serial data (sda) 19 io p1[2] 20 io p1[4] optional external clock input (extclk) 21 io p1[6] 22 io p3[0] 23 io p3[2] 24 io p3[4] 25 io p3[6] 26 input xres active high external reset with internal pull down. 27 io p4[0] 28 io p4[2] 29 io p4[4] 30 io p4[6] 31 io i p2[0] direct switched capacitor block input. 32 io i p2[2] direct switched capacitor block input. 33 io p2[4] external analog ground (agnd) 34 io p2[6] external voltage reference (vref) 35 io i p0[0] analog column mux input. 36 io io p0[2] analog column mux input and column output. 37 io io p0[4] analog column mux input and column output. 38 io i p0[6] analog column mux input. 39 power vdd supply voltage. 40 io i p0[7] analog column mux input. 41 io io p0[5] analog column mux input and column output. 42 io io p0[3] analog column mux input and column output. 43 io i p0[1] analog column mux input. 44 io p2[7] legend : a = analog, i = input, and o = output. tqfp p3[1] p2[7] p2[5] p2[4], external agn d a i, p2[3] p2[2], ai a i, p2[1] p2[0], ai p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] smp xres p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] i2c scl, p1[7] p0[1], ai i2c sda, p1[5] p0[3], aio p1[3] p0[5], aio i2c scl, xtalin, p1[1] p0[7], ai vss vdd i2c sda, xtalout, p1[0] p0[6], ai p1[2] p0[4], aio extclk, p1[4] p0[2], aio p1[6] p0[0], ai p3[0] p2[6], external vre f 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 13 14 15 16 17 18 19 20 21 22 12
august 3, 2004 document no. 38-12012 rev. *i 12 cy8c27x43 final data sheet 1. pin information 1.1.5 48-pin part pinouts table 1-5. 48-pin part pinout (ssop) pin no. type pin name description cy8c27643 48-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 io p4[7] 10 io p4[5] 11 io p4[3] 12 io p4[1] 13 power smp switch mode pump (smp) connection to external components required. 14 io p3[7] 15 io p3[5] 16 io p3[3] 17 io p3[1] 18 io p5[3] 19 io p5[1] 20 io p1[7] i2c serial clock (scl) 21 io p1[5] i2c serial data (sda) 22 io p1[3] 23 io p1[1] crystal input (xtalin), i2c serial clock (scl) 24 power vss ground connection. 25 io p1[0] crystal output (xtalout), i2c serial data (sda) 26 io p1[2] 27 io p1[4] optional external clock input (extclk) 28 io p1[6] 29 io p5[0] 30 io p5[2] 31 io p3[0] 32 io p3[2] 33 io p3[4] 34 io p3[6] 35 input xres active high external reset with internal pull down. 36 io p4[0] 37 io p4[2] 38 io p4[4] 39 io p4[6] 40 io i p2[0] direct switched capacitor block input. 41 io i p2[2] direct switched capacitor block input. 42 io p2[4] external analog ground (agnd) 43 io p2[6] external voltage reference (vref) 44 io i p0[0] analog column mux input. 45 io io p0[2] analog column mux input and column output. 46 io io p0[4] analog column mux input and column output. 47 io i p0[6] analog column mux input. 48 power vdd supply voltage. legend : a = analog, i = input, and o = output. ssop ai, p0[7] vdd aio, p0[5] p0[6], ai aio, p0[3] p0[4], aio ai, p0[1] p0[2], aio p2[7] p0[0], ai p2[5] p2[6], external vref ai, p2[3] p2[4], external agnd ai, p2[1] p2[2], ai p4[7] p2[0], ai p4[5] p4[6] p4[3] p4[4] p4[1] p4[2] smp p4[0] p3[7] xres p3[5] p3[6] p3[3] p3[4] p3[1] p3[2] p5[3] p3[0] p5[1] p5[2] i2c scl, p1[7] p5[0] i2c sda, p1[5] p1[6] p1[3] p1[4], extclk i 2c scl, xtalin, p1[1] p1[2] vss p1[0], xtalout, i2c sd a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25
august 3, 2004 document no. 38-12012 rev. *i 13 cy8c27x43 final data sheet 1. pin information table 1-6. 48-pin part pinout (mlf*) pin no. type pin name description cy8c27643 48-pin psoc device digital analog 1 io i p2[3] direct switched capacitor block input. 2 io i p2[1] direct switched capacitor block input. 3 io p4[7] 4 io p4[5] 5 io p4[3] 6 io p4[1] 7 power smp switch mode pump (smp) connection to external components required. 8 io p3[7] 9 io p3[5] 10 io p3[3] 11 io p3[1] 12 io p5[3] 13 io p5[1] 14 io p1[7] i2c serial clock (scl) 15 io p1[5] i2c serial data (sda) 16 io p1[3] 17 io p1[1] crystal input (xtalin), i2c serial clock (scl) 18 power vss ground connection. 19 io p1[0] crystal output (xtalout), i2c serial data (sda) 20 io p1[2] 21 io p1[4] optional external clock input (extclk) 22 io p1[6] 23 io p5[0] 24 io p5[2] 25 io p3[0] 26 io p3[2] 27 io p3[4] 28 io p3[6] 29 input xres active high external reset with internal pull down. 30 io p4[0] 31 io p4[2] 32 io p4[4] 33 io p4[6] 34 io i p2[0] direct switched capacitor block input. 35 io i p2[2] direct switched capacitor block input. 36 io p2[4] external analog ground (agnd) 37 io p2[6] external voltage reference (vref) 38 io i p0[0] analog column mux input. 39 io io p0[2] analog column mux input and column output. 40 io io p0[4] analog column mux input and column output. 41 io i p0[6] analog column mux input. 42 power vdd supply voltage. 43 io i p0[7] analog column mux input. 44 io io p0[5] analog column mux input and column output. 45 io io p0[3] analog column mux input and column output. 46 io i p0[1] analog column mux input. 47 io p2[7] 48 io p2[5] legend : a = analog, i = input, and o = output. * the mlf package has a center pad that must be connected to ground (vss). mlf (top view) p2[5] p2[7] p0[1], ai p0[3], aio p0[5], aio p0[7], ai vdd p0[6], ai p0[4], aio p0[2], aio p0[0], ai p2[6], external vre f 10 11 12 a i, p2[3] a i, p2[1] p4[7] p4[5] p4[3] p4[1] smp p3[7] p3[5] p3[3] p3[1] p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[2], ai p2[0], ai p4[6] p4[4] p4[2] p4[0] xres p3[6] p3[4] p3[2] p3[0] p2[4], external agn d 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p5[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] p1[6] p5[0] p5[2]
august 3, 2004 ? cypress microsystems, inc. 2003 ? document no. 38-12012 rev. *i 14 2. register reference this chapter lists the registers of the cy8c27x43 psoc device. for detailed register information, reference the psoc? mixed sig- nal array technical reference manual . 2.1 register conventions the register conventions specific to this section are listed in the following table. 2.2 register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
august 3, 2004 document no. 38-12012 rev. *i 15 cy8c27x43 final data sheet 2. register reference register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 asc12cr0 88 rw c8 prt2ie 09 rw 49 asc12cr1 89 rw c9 prt2gs 0a rw 4a asc12cr2 8a rw ca prt2dm2 0b rw 4b asc12cr3 8b rw cb prt3dr 0c rw 4c asd13cr0 8c rw cc prt3ie 0d rw 4d asd13cr1 8d rw cd prt3gs 0e rw 4e asd13cr2 8e rw ce prt3dm2 0f rw 4f asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw d0 prt4ie 11 rw 51 asd20cr1 91 rw d1 prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw d3 prt5dr 14 rw 54 asc21cr0 94 rw d4 prt5ie 15 rw 55 asc21cr1 95 rw d5 prt5gs 16 rw 56 asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c_scr d7 # 18 58 asd22cr0 98 rw i2c_dr d8 rw 19 59 asd22cr1 99 rw i2c_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw dc 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 a8 mul_x e8 w dcb02dr1 29 w 69 a9 mul_y e9 w dcb02dr2 2a rw 6a aa mul_dh ea r dcb02cr0 2b # 6b ab mul_dl eb r dcb03dr0 2c # 6c ac acc_dr1 ec rw dcb03dr1 2d w 6d ad acc_dr0 ed rw dcb03dr2 2e rw 6e ae acc_dr3 ee rw dcb03cr0 2f # 6f af acc_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdiolt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
august 3, 2004 document no. 38-12012 rev. *i 16 cy8c27x43 final data sheet 2. register reference register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 asc10cr0 80 rw c0 prt0dm1 01 rw 41 asc10cr1 81 rw c1 prt0ic0 02 rw 42 asc10cr2 82 rw c2 prt0ic1 03 rw 43 asc10cr3 83 rw c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 asc12cr0 88 rw c8 prt2dm1 09 rw 49 asc12cr1 89 rw c9 prt2ic0 0a rw 4a asc12cr2 8a rw ca prt2ic1 0b rw 4b asc12cr3 8b rw cb prt3dm0 0c rw 4c asd13cr0 8c rw cc prt3dm1 0d rw 4d asd13cr1 8d rw cd prt3ic0 0e rw 4e asd13cr2 8e rw ce prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw 50 asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw 51 asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw 54 asc21cr0 94 rw d4 prt5dm1 15 rw 55 asc21cr1 95 rw d5 prt5ic0 16 rw 56 asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 18 58 asd22cr0 98 rw d8 19 59 asd22cr1 99 rw d9 1a 5a asd22cr2 9a rw da 1b 5b asd22cr3 9b rw db 1c 5c asc23cr0 9c rw dc 1d 5d asc23cr1 9d rw osc_go_en dd rw 1e 5e asc23cr2 9e rw osc_cr4 de rw 1f 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw 6c ac ec dcb03in 2d rw 6d ad ed dcb03ou 2e rw 6e ae ee 2f 6f af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdiolt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fa 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
august 3, 2004 document no. 38-12012 rev. *i 17 3. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c27x43 psoc device. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. specifications for devices running at greater than 12 mhz are valid for -40 o c t a 70 o c and t j 82 o c. figure 3-1. voltage versus cpu frequency the following table lists the units of measure that are used in this chapter. 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l i d o p e r a t i n g r e g i o n table 3-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius w micro watts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nano ampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm ? ohm mhz megahertz pa pico ampere m ? megaohm pf pico farad a micro ampere pp peak-to-peak f micro farad ppm parts per million h micro henry ps picosecond s microsecond sps samples per second v micro volts sigma: one standard deviation vrms micro volts root-mean-square v volts
august 3, 2004 document no. 38-12012 rev. *i 18 cy8c27x43 final data sheet 3. electrical specifications 3.1 absolute maximum ratings 3.2 operating temperature table 3-2. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 o c higher storage temperatures will reduce data retention time. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss- 0.5 ? vdd + 0.5 v ? dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma i maio maximum current into any port pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd ? latch-up current ? ? 200 ma table 3-3. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 41 . the user must limit the power con- sumption to comply with this requirement.
august 3, 2004 document no. 38-12012 rev. *i 19 cy8c27x43 final data sheet 3. electrical specifications 3.3 dc electrical characteristics 3.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 3.3.2 dc general purpose io specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-4. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current ? 5 8 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, 48 mhz = disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz. i dd3 supply current ? 3.3 6.0 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, 48 mhz = disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. a a. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled. ? 3 6.5 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, -40 o c t a 55 o c. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. a ? 4 25 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, 55 o c < t a 85 o c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. a ? 4 7.5 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40 o c t a 55 o c. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. a ? 5 26 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, 55 o c < t a 85 o c. v ref reference voltage (bandgap) for silicon a b b. refer to the ordering information chapter on page 42 . 1.275 1.300 1.325 v trimmed for appropriate vdd. v ref reference voltage (bandgap) for silicon b b 1.280 1.300 1.320 v trimmed for appropriate vdd. table 3-5. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k ? r pd pull down resistor 4 5.6 8 k ? v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c.
august 3, 2004 document no. 38-12012 rev. *i 20 cy8c27x43 final data sheet 3. electrical specifications 3.3.3 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched cap psoc blocks. the guaranteed specifications are measured in the analog continuous time psoc block. typical parameters apply to 5v at 25 c and are for design guidance only. table 3-6. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? vdd vdd - 0.5 v the common-mode input voltage range is mea- sured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? cmrr oa common mode rejection ratio power = low power = medium power = high 60 60 60 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. g oloa open loop gain power = low power = medium power = high 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low power = medium power = high vdd - 0.2 vdd - 0.2 vdd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low power = medium power = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 60 ? ? db 0v v in (vdd - 2.25) or (vdd - 1.25v) v in vdd .
august 3, 2004 document no. 38-12012 rev. *i 21 cy8c27x43 final data sheet 3. electrical specifications table 3-7. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.2 ? vdd - 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrr oa common mode rejection ratio power = low power = medium power = high 50 50 50 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. g oloa open loop gain power = low power = medium power = high 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low power = medium power = high is 5v only vdd - 0.2 vdd - 0.2 vdd - 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low power = medium power = high ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 50 ? ? db 0v v in (vdd - 2.25) or (vdd - 1.25v) v in vdd .
august 3, 2004 document no. 38-12012 rev. *i 22 cy8c27x43 final data sheet 3. electrical specifications 3.3.4 dc analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-8. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.3 0.5 x vdd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 60 ? ? db table 3-9. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 60 ? ? db
august 3, 2004 document no. 38-12012 rev. *i 23 cy8c27x43 final data sheet 3. electrical specifications 3.3.5 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-2. basic switch mode pump circuit table 3-10. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5v 5v output voltage 4.75 5.0 5.25 v configuration of footnote a . average, neglecting ripple. smp trip voltage is set to 5.0v. a. l 1 = 2 h inductor, c 1 = 10 f capacitor, d 1 = schottky diode. see figure 3-2. v pump 3v 3v output voltage 3.00 3.25 3.60 v configuration of footnote a . average, neglecting ripple. smp trip voltage is set to 3.25v. i pump available output current v bat = 1.5v, v pump = 3.25v v bat = 1.8v, v pump = 5.0v 8 5 ? ? ? ? ma ma configuration of footnote a . smp trip voltage is set to 3.25v. smp trip voltage is set to 5.0v. v bat 5v input voltage range from battery 1.8 ? 5.0 v configuration of footnote a . smp trip voltage is set to 5.0v. v bat 3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote a . smp trip voltage is set to 3.25v. v batstart minimum input voltage from battery to start pump 1.1 ? ? v configuration of footnote a . ? v pump_line line regulation (over v bat range) ? 5 ? %v o configuration of footnote a . v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 3-16 on page 26 . ? v pump_load load regulation ? 5 ? %v o configuration of footnote a . v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 3-16 on page 26 . ? v pump_ripple output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configuration of footnote a . load is 5ma. e 3 efficiency 35 50 ? % configuration of footnote a . load is 5 ma. smp trip voltage is set to 3.25v. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % battery c1 d1 + psoc tm vdd vss smp v bat v pum p l 1
august 3, 2004 document no. 38-12012 rev. *i 24 cy8c27x43 final data sheet 3. electrical specifications 3.3.6 dc analog reference specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the guaranteed specifications are measured through the analog continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 3-11. silicon revision a ? 5v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.274 1.30 1.326 v ? agnd = vdd/2 a a. agnd tolerance includes the offsets of the local buffer in the psoc block. vdd/2 - 0.030 vdd/2 - 0.004 vdd/2 + 0.003 v ? agnd = 2 x bandgap a 2 x bg - 0.043 2 x bg - 0.010 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) a p2[4] - 0.013 p2[4] p2[4] + 0.014 v ? agnd = bandgap a bg - 0.009 bg bg + 0.009 v ? agnd = 1.6 x bandgap a 1.6 x bg - 0.018 1.6 x bg 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd /2 + bg - 0.140 vdd /2 + bg - 0.018 vdd /2 + bg + 0.103 v ? refhi = 3 x bandgap 3 x bg - 0.112 3 x bg - 0.018 3 x bg + 0.076 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) 2 x bg + p2[6] - 0.113 2 x bg + p2[6] - 0.018 2 x bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg - 0.130 p2[4] + bg - 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.133 p2[4] + p2[6] - 0.016 p2[4] + p2[6] + 0.100 v ? refhi = 3.2 x bandgap 3.2 x bg - 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = vdd/2 ? bandgap vdd /2 - bg - 0.051 vdd /2 - bg + 0.024 vdd /2 - bg + 0.098 v ? reflo = bandgap bg - 0.082 bg + 0.023 bg + 0.129 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2 x bg - p2[6] - 0.084 2 x bg - p2[6] + 0.025 2 x bg - p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - bg - 0.056 p2[4] - bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.057 p2[4] - p2[6] + 0.026 p2[4] - p2[6] + 0.110 v table 3-12. silicon revision b ? 5v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 a a. agnd tolerance includes the offsets of the local buffer in the psoc block. vdd/2 - 0.030 vdd/2 vdd/2 + 0.007 v ? agnd = 2 x bandgap a 2 x bg - 0.043 2 x bg 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) a p2[4] - 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap a bg - 0.009 bg bg + 0.009 v ? agnd = 1.6 x bandgap a 1.6 x bg - 0.018 1.6 x bg 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd /2 + bg - 0.1 vdd /2 + bg - 0.01 vdd /2 + bg + 0.1 v ? refhi = 3 x bandgap 3 x bg - 0.06 3 x bg - 0.01 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) 2 x bg + p2[6] - 0.06 2 x bg + p2[6] - 0.01 2 x bg + p2[6] + 0.06 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg - 0.06 p2[4] + bg - 0.01 p2[4] + bg + 0.06 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.06 p2[4] + p2[6] - 0.01 p2[4] + p2[6] + 0.06 v ? refhi = 3.2 x bandgap 3.2 x bg - 0.06 3.2 x bg - 0.01 3.2 x bg + 0.06 v ? reflo = vdd/2 ? bandgap vdd /2 - bg - 0.051 vdd /2 - bg + 0.01 vdd /2 - bg + 0.06 v ? reflo = bandgap bg - 0.06 bg + 0.01 bg + 0.06 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2 x bg - p2[6] - 0.04 2 x bg - p2[6] + 0.01 2 x bg - p2[6] + 0.04 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - bg - 0.056 p2[4] - bg + 0.01 p2[4] - bg + 0.056 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.056 p2[4] - p2[6] + 0.01 p2[4] - p2[6] + 0.056 v
august 3, 2004 document no. 38-12012 rev. *i 25 cy8c27x43 final data sheet 3. electrical specifications table 3-13. silicon revision a ? 3.3v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.274 1.30 1.326 v ? agnd = vdd/2 a a. agnd tolerance includes the offsets of the local buffer in the psoc block. note see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimmi ng for operation at 3.3v. vdd/2 - 0.027 vdd/2 - 0.003 vdd/2 + 0.002 v ? agnd = 2 x bandgap a not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap a bg - 0.009 bg bg + 0.009 v ? agnd = 1.6 x bandgap a 1.6 x bg - 0.018 1.6 x bg 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.075 p2[4] + p2[6] - 0.009 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.048 p2[4] - p2[6] + 0.022 p2[4] - p2[6] + 0.092 v table 3-14. silicon revision b ? 3.3v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 a a. agnd tolerance includes the offsets of the local buffer in the psoc block. note see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimmi ng for operation at 3.3v. vdd/2 - 0.027 vdd/2 vdd/2 + 0.005 v ? agnd = 2 x bandgap a not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.008 p2[4] p2[4] + 0.009 v ? agnd = bandgap a bg - 0.009 bg bg + 0.009 v ? agnd = 1.6 x bandgap a 1.6 x bg - 0.018 1.6 x bg 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.06 p2[4] + p2[6] - 0.01 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.048 p2[4] - p2[6] + 0.01 p2[4] - p2[6] + 0.048 v
august 3, 2004 document no. 38-12012 rev. *i 26 cy8c27x43 final data sheet 3. electrical specifications 3.3.7 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 3.3.8 dc por and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc mixed signal array technical reference manual for more information on the vlt_cr register. table 3-15. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switch cap) ? 80 ? ff table 3-16. dc por and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lv d0 v lv d1 v lv d2 v lv d3 v lv d4 v lv d5 v lv d6 v lv d7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 a 3.08 3.20 4.08 4.57 4.74 b 4.82 4.91 a. always greater than 50 mv above ppor (porlev = 00) for falling supply. b. always greater than 50 mv above ppor (porlev = 10) for falling supply. v v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 v v v v v v v v v
august 3, 2004 document no. 38-12012 rev. *i 27 cy8c27x43 final data sheet 3. electrical specifications 3.3.9 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-17. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? ye ar s
august 3, 2004 document no. 38-12012 rev. *i 28 cy8c27x43 final data sheet 3. electrical specifications 3.4 ac electrical characteristics 3.4.1 ac chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-3. pll lock timing diagram table 3-18. ac chip-level specifications symbol description min typ max units notes f imo internal main oscillator frequency 23.4 24 24.6 a mhz trimmed. utilizing factory trim values. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz trimmed. utilizing factory trim values. f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b,c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for in formation on trimming for operation at 3.3v. mhz trimmed. utilizing factory trim values. f 48m digital psoc block frequency 0 48 49.2 a,b,d d. see the individual user module data sheets for information on maximum frequencies for user modules. mhz refer to the ac digital block specifications below. f 24m digital psoc block frequency 0 24 24.6 b, d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.986 ? mhz multiple (x732) of crystal frequency. jitter24m2 24 mhz period jitter (pll) ? ? 600 ps t pllslew pll lock time 0.5 ? 10 ms t pllslews- low pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 1700 2620 ms t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 uw maximum drive level 32.768 khz crystal. 3.0v vdd 5.5v, -40 o c t a 85 o c. jitter32k 32 khz period jitter ? 100 ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s 24 mhz f pll pll e nable t pllslew pll gain 0
august 3, 2004 document no. 38-12012 rev. *i 29 cy8c27x43 final data sheet 3. electrical specifications figure 3-4. pll lock for low gain setting timing diagram figure 3-5. external crystal oscillator startup timing diagram figure 3-6. 24 mhz period jitter (imo) timing diagram figure 3-7. 32 khz period jitter (eco) timing diagram 24 mhz f pll pll e nable t pllslewlow pll gain 1 32 khz f 32k2 32k s elect t os jitter24m1 f 24m jitter32k f 32k2
august 3, 2004 document no. 38-12012 rev. *i 30 cy8c27x43 final data sheet 3. electrical specifications 3.4.2 ac general purpose io specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-8. gpio timing diagram table 3-19. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls trisef trises 90% 10% gpio pin output v oltage
august 3, 2004 document no. 38-12012 rev. *i 31 cy8c27x43 final data sheet 3. electrical specifications 3.4.3 ac operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v. table 3-20. 5v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 3-21. 3.3v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = low, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz
august 3, 2004 document no. 38-12012 rev. *i 32 cy8c27x43 final data sheet 3. electrical specifications 3.4.4 ac digital block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-22. ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 3.0v < vdd < 4.75v. timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 24.6 mhz counter enable pulse width 50 a ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 a ? ? ns disable mode 50 a ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 ns width of ss_ negated between transmissions 50 a ? ? ns transmitter maximum input clock frequency b silicon a silicon b b. refer to the ordering information chapter on page 42 . ? ? ? ? 16.4 24.6 mhz mhz maximum data rate at 2.05 mhz due to 8 x over clocking. maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency b silicon a silicon b ? ? ? ? 16.4 24.6 mhz mhz maximum data rate at 2.05 mhz due to 8 x over clocking. maximum data rate at 3.08 mhz due to 8 x over clocking.
august 3, 2004 document no. 38-12012 rev. *i 33 cy8c27x43 final data sheet 3. electrical specifications 3.4.5 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-23. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz table 3-24. 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz
august 3, 2004 document no. 38-12012 rev. *i 34 cy8c27x43 final data sheet 3. electrical specifications 3.4.6 ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 3.4.7 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-25. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 3-26. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 a a. maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum f requency and duty cycle requirements. 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater b b. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this cas e, the cpu clock divider will ensure that the fifty per- cent duty cycle requirement is met. 0.186 ?24.6mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 3-27. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 10 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6
august 3, 2004 document no. 38-12012 rev. *i 35 cy8c27x43 final data sheet 3. electrical specifications 3.4.8 ac i 2 c specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-9. definition for timing for fast/standard mode on the i 2 c bus table 3-28. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns s da scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
august 3, 2004 ? cypress microsystems, inc. 2003 ? document no. 38-12012 rev. *i 36 4. packaging information this chapter illustrates the packaging specifications for the cy8c27x43 psoc device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support/link.cfm?mr=poddim . 4.1 packaging dimensions figure 4-1. 8-lead (300-mil) pdip 51-85075 - *a
august 3, 2004 document no. 38-12012 rev. *i 37 cy8c27x43 final data sheet 4. packaging information figure 4-2. 20-lead (210-mil) ssop figure 4-3. 20-lead (300-mil) molded soic 51-85077 - *c 51-85024 - *b
august 3, 2004 document no. 38-12012 rev. *i 38 cy8c27x43 final data sheet 4. packaging information figure 4-4. 28-lead (300-mil) molded dip figure 4-5. 28-lead (210-mil) ssop 51-85014 - *d 51-85079 - *c
august 3, 2004 document no. 38-12012 rev. *i 39 cy8c27x43 final data sheet 4. packaging information figure 4-6. 28-lead (300-mil) molded soic figure 4-7. 44-lead tqfp 51-85026 - *c 51-85064-b 51-85064 - *b
august 3, 2004 document no. 38-12012 rev. *i 40 cy8c27x43 final data sheet 4. packaging information figure 4-8. 48-lead (300-mil) ssop figure 4-9. 48-lead (7x7 mm) mlf 51-85061-c 51-85061 - *c 0.80 dia. 6.70 6.90 c 1.00 max. n seating plane n 2 2 0.230.05 0.50 1 1 0.08 0-12 0.30-0.45 0.05 max. c 0.20 ref. 0.80 max. pin1 id 5.45 0.420.18 (4x) 7.10 6.80 6.70 6.80 7.10 6.90 5.55 5.45 5.55 0.20 r. 0.45 y x top view bottom view side view e-pad dimensions in mm min. max. e-pad size paddle size 51x51 53x53 (x, y max.) 51-85152 - *b
august 3, 2004 document no. 38-12012 rev. *i 41 cy8c27x43 final data sheet 4. packaging information 4.2 thermal impedances 4.3 capacitance on crystal pins table 4-1. thermal impedances per package package typical ja * 8 pdip 120 o c/w 20 ssop 95 o c/w 20 soic 79 o c/w 28 pdip 67 o c/w 28 ssop 95 o c/w 28 soic 71 o c/w 44 tqfp 58 o c/w 48 ssop 69 o c/w 48 mlf 18 o c/w * t j = t a + power x ja table 4-2: typical package capacitance on crystal pins package package capacitance 8 pdip 2.8 pf 20 ssop 2.6 pf 20 soic 2.5 pf 28 pdip 3.5 pf 28 ssop 2.8 pf 28 soic 2.7 pf 44 tqfp 2.6 pf 48 ssop 3.3 pf 48 mlf 2.3 pf
august 3, 2004 document no. 38-12012 rev. *i 42 5. ordering information the following table lists the cy8c27x43 psoc device family?s key package features and ordering codes. table 5-1. cy8c27x43 psoc device family key features and ordering information package ordering code flash (kbytes) ram (bytes) switch mode pump temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital io pins analog inputs analog outputs xres pin cy8c27x43 silicon b ? these parts are lead free and offer the following improvements. the dec_cr1 register selections are enhanced to allow any digital block to be the decimator clock source, the eco ex and eco exw bits in the cpu_scr1 register are readable, and the accuracy of the analog reference is enhanced (see the electrical specifications chapter). all silicon a errata are fixed in silicon b. 8 pin (300 mil) dip cy8c27143-24pxi 16 256 no -40c to +85c 8 12 6 4 4 no 20 pin (210 mil) ssop cy8c27243-24pvxi 16 256 yes -40c to +85c 8 12 16 8 4 yes 20 pin (210 mil) ssop (tape and reel) cy8c27243-24pvxit 16 256 yes -40c to +85c 8 12 16 8 4 yes 20 pin (300 mil) soic cy8c27243-24sxi 16 256 yes -40c to +85c 8 12 16 8 4 yes 20 pin 300 mil) soic (tape and reel) cy8c27243-24sxit 16 256 yes -40c to +85c 8 12 16 8 4 yes 28 pin (300 mil) dip cy8c27443-24pxi 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (210 mil) ssop cy8c27443-24pvxi 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (210 mil) ssop (tape and reel) cy8c27443-24pvxit 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (300 mil) soic cy8c27443-24sxi 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (300 mil) soic (tape and reel) cy8c27443-24sxit 16 256 yes -40c to +85c 8 12 24 12 4 yes 44 pin tqfp cy8c27543-24axi 16 256 yes -40c to +85c 8 12 40 12 4 yes 44 pin tqfp (tape and reel) cy8c27543-24axit 16 256 yes -40c to +85c 8 12 40 12 4 yes 48 pin (300 mil) ssop cy8c27643-24pvxi 16 256 yes -40c to +85c 8 12 44 12 4 yes 48 pin (300 mil) ssop (tape and reel) cy8c27643-24pvxit 16 256 yes -40c to +85c 8 12 44 12 4 yes 48 pin (7x7) mlf cy8c27643-24lfxi 16 256 yes -40c to +85c 8 12 44 12 4 yes 48 pin (7x7) mlf (tape and reel) CY8C27643-24LFXIT 16 256 yes -40c to +85c 8 12 44 12 4 yes cy8c27x43 silicon a ? silicon a is not recommended for new designs. 8 pin (300 mil) dip cy8c27143-24pi 16 256 no -40c to +85c 8 12 6 4 4 no 20 pin (210 mil) ssop cy8c27243-24pvi 16 256 yes -40c to +85c 8 12 16 8 4 yes 20 pin (210 mil) ssop (tape and reel) cy8c27243-24pvit 16 256 yes -40c to +85c 8 12 16 8 4 yes 20 pin (300 mil) soic cy8c27243-24si 16 256 yes -40c to +85c 8 12 16 8 4 yes 20 pin 300 mil) soic (tape and reel) cy8c27243-24sit 16 256 yes -40c to +85c 8 12 16 8 4 yes 28 pin (300 mil) dip cy8c27443-24pi 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (210 mil) ssop cy8c27443-24pvi 16 256 yes -40c to +85c 8 12 24 12 4 yes
august 3, 2004 document no. 38-12012 rev. *i 43 cy8c27x43 final data sheet 5. ordering information 5.1 ordering code definitions 28 pin (210 mil) ssop (tape and reel) cy8c27443-24pvit 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (300 mil) soic cy8c27443-24si 16 256 yes -40c to +85c 8 12 24 12 4 yes 28 pin (300 mil) soic (tape and reel) cy8c27443-24sit 16 256 yes -40c to +85c 8 12 24 12 4 yes 44 pin tqfp cy8c27543-24ai 16 256 yes -40c to +85c 8 12 40 12 4 yes 44 pin tqfp (tape and reel) cy8c27543-24ait 16 256 yes -40c to +85c 8 12 40 12 4 yes 48 pin (300 mil) ssop cy8c27643-24pvi 16 256 yes -40c to +85c 8 12 44 12 4 yes 48 pin (300 mil) ssop (tape and reel) cy8c27643-24pvit 16 256 yes -40c to +85c 8 12 44 12 4 yes 48 pin (7x7) mlf cy8c27643-24lfi 16 256 yes -40c to +85c 8 12 44 12 4 yes 48 pin (7x7) mlf (tape and reel) cy8c27643-24lfit 16 256 yes -40c to +85c 8 12 44 12 4 yes table 5-1. cy8c27x43 psoc device family key features and ordering information (continued) package ordering code flash (kbytes) ram (bytes) switch mode pump temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital io pins analog inputs analog outputs xres pin c y 8 c 27 xxx-spxx package type: thermal rating: p = pdip px = pdip pb free c = commercial s = soic sx = soic pb free i = industrial pv = ssop pvx = ssop pb free e = extended lf = mlf lfx = mlf pb free a = tqfp ax = tqfp pb free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress microsystems company id: cy = cypress
august 3, 2004 ? cypress microsystems, inc. 2002 ? 2004 ? document no. 38-12012 rev. *i 44 6. sales and service information to obtain information about cypress microsystems or psoc sales and technical support, reference the following information or go to the section titled ?getting started? on page 4 in this document. cypress microsystems 6.1 revision history 6.2 copyrights and code protection copyrights ? cypress microsystems, inc. 2000 ? 2004. all rights reserved. psoc?, psoc designer?, and programmable system-on-chip? are trad emarks of cypress microsys- tems, inc. all other trademarks or registered trademarks referenced herein are property of the respective corporations. the information contained herein is subject to change without notice. cypress microsystems assumes no responsibility for the us e of any circuitry other than circuitry embodied in a cypress microsystems product. nor does it convey or imply any license under patent or other rights. cypress micro systems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in s ignificant injury to the user. the inclusion of cypress microsystems products in life-support systems application implies that the manufacturer assumes all risk of such use an d in doing so indemnifies cypress microsystems against all charges. cypress microsystems products are not warranted nor intended to be used for medical, life-sup port, life-saving, critical control or safety applications, unless pursuant to an express written agreement with cypress microsystems. flash code protection note the following details of the flash code protection features on cypress microsystems devices. cypress microsystems products meet the specifications contained in their particular cypress microsystems data sheets. cypress m icrosystems believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be meth ods, unknown to cypress microsystems, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress microsystems nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteei ng the product as "unbreakable." cypress microsystems is willing to work with the customer who is concerned about the integrity of their code. code protection i s constantly evolving. we at cypress micro- systems are committed to continuously improving the code protection features of our products. 2700 162nd street sw building d lynnwood, wa 98037 phone: 800.669.0557 facsimile: 425.787.4641 web sites: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm table 6-1. cy8c27x43 data sheet revision history document title: cy8c27143, cy8c27243, cy8c27443, cy8c27543, and cy8c27643 psoc mixed signal array final data sheet document number: 38-12012 revision ecn # issue date origin of change description of change ** 127087 7/01/2003 new silicon. new document (revision **). *a 128780 7/29/2003 engineering and nwj. new electrical spec additions, fix of core architecture links, corrections to some text, tables, draw- ings, and format. *b 128992 8/14/2003 nwj interrupt controller table fixed, refinements to electrical spec section and register chapter. *c 129283 8/28/2003 nwj significant changes to the electrical specifications section. *d 129442 9/09/2003 nwj changes made to electrical spec section. added 20/28-lead soic packages and pinouts. *e 130129 10/13/2003 nwj revised document for silicon revision a. *f 130651 10/28/2003 nwj refinements to electrical specification section and i2c chapter. *g 131298 11/18/2003 nwj revisions to gdi, rdi, and digital block chapters. revisions to ac digital block spec and miscella- neous register changes. *h 229416 see ecn sfv new data sheet format and organization. reference the psoc mixed signal array technical refer- ence manual for additional information. title change. *i 247529 see ecn sfv added silicon b information to this data sheet. distribution : external public posting : none

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